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? ? high \ efficiency ? 5v ? mosfet ? gate ? driver ? CHL8505 ? december ? 6, ? 2011 ?? | ?? final ? | ?? v1.05 1 features ? ? ideal ? for ? server ? memory ? applications ? using ? +5v ?? ? fixed ? 5v ? gate ? drive ?? ? large ? drivers ? designed ? to ? drive ? 3nf ? in ? < ? 15ns ?? with ? +5v ? drive ? ? low \ side ? driver ? ? ? 2a ? source/4a ? sink ?? ? high \ side ? driver ? ? ? 2a ? source/2a ? sink ?? ? transitions ? times ? & ? propagation ? delays ? < ? 15ns ? ? integrated ? bootstrap ? diode ?? ? capable ? of ? high ? switching ? frequencies ? from ? 200khz ? up ? to ? greater ? than ? 1mhz ? ? compatible ? with ? ir?s ? patented ? active ? tri \ level ? (atl) ? pwm ? for ? fastest ? response ? to ? transient ? overshoot ? ? non \ overlap ? and ? under ? voltage ? protection ? ? thermally ? enhanced ? 10 \ pin ? dfn ? package ? ? lead ? free ? rohs ? compliant ? package ? ? low ? quiescent ? power ? to ? optimize ? efficiency ? applications ? ? multiphase ? synchronous ? buck ? converter ? for ? server ? cpus ? and ? ddr ? memory ? vr ? solutions ? ? high ? efficiency ? and ? compact ? vrm ? ? optimized ? for ? sleep ? state ? s3 ? systems ? using ? +5vsb ? ? notebook ? computer ? and ? graphics ? vr ? solutions ? basic ? application ? ? ? figure ? 1: ? CHL8505 ? basic ? application ? circuit ? description ? the ? CHL8505 ? mosfet ? is ? a ? high \ efficiency ? gate ? driver ? which ? can ? switch ? both ? high \ side ? and ? low \ side ? n \ channel ? external ? mosfets ? in ? a ? synchronous ? buck ? converter. ? it ? is ? intended ? for ? use ? with ? ir ? digital ? pwm ? controllers ? to ? provide ? a ? total ? voltage ? regulator ? (vr) ? solution ? for ? today?s ? advanced ? computing ? applications. ?? the ? CHL8505 ? driver ? is ? capable ? of ? rapidly ? switching ? large ? mosfets ? with ? low ? r dson ? and ? large ? input ? capacitance ? used ? in ? high \ efficiency ? designs. ? it ? is ? uniquely ? designed ? to ? operate ? from ? a ? 5v ? source ? such ? as ? a ? system ? 5v ? or ? 5v ? standby ? voltages ? in ? sleep ? states. ??? the ? CHL8505 ? has ? a ? unique ? circuit ? which ? improves ? drive ? strength ? to ? the ? external ? mosfets ? even ? with ? just ? 5v ? supplied ? at ? the ? vdrv ? pin. ? this ? insures ? faster ? switching ? comparable ? to ? drivers ? designed ? for ? +12v ? drive ? operation. ? the ? integrated ? boot ? diode ? reduces ? external ? component ? count. ? the ? CHL8505 ? also ? features ? an ? adaptive ? non \ overlap ? control ? for ? shoot \ through ? protection. ? the ? CHL8505 ? is ? configured ? to ? drive ? both ? the ? high ? and ? low \ side ? switches ? from ? the ? patented ? ir ? fast ? active ? tri \ level ? (atl) ? pwm ? signal, ? which ? will ? optimize ? the ? turn ? off ? time ? of ? individual ? phases, ? optimizing ? transient ? performance. ? pin ? diagram ? ? top view gnd pin 11 3x3 dfn nc boot lo_gate hi_gate nc pwm vcc nc switch vdrv 6 7 8 9 10 5 4 3 2 1 ? figure ? 2: ? CHL8505 ? package ? top ? view ?
? ? high \ efficiency ? 5v ? mosfet ? gate ? driver ? CHL8505 ? december ? 6, ? 2011 ?? | ?? final ? | ?? v1.05 2 ordering ? information ? ???????? CHL8505 ? ? ? ? ? ?? ??????? ? ? ? ? package ? tape ? & ? reel ? qty ? part ? number ? dfn ? 3000 ? CHL8505crt ? ? ? ? ? ? ? ? ? ? top view gnd pin 11 3x3 dfn nc boot lo_gate hi_gate nc pwm vcc nc switch vdrv 6 7 8 9 10 5 4 3 2 1 ? figure ? 3: ? CHL8505 ? pin ? diagram ? enlarged t ? ? ? tape ? and ? reel ?? ? r ? ? ? package ? type ? (dfn) ? ? c ? ? ? operating ? temperature ? (commercial ? standard) ?
? ? high \ efficiency ? 5v ? mosfet ? gate ? driver ? CHL8505 ? december ? 6, ? 2011 ?? | ?? final ? | ?? v1.05 3 functional ? block ? diagram ? ? ? figure ? 4: ? CHL8505 ? simplified ? functional ? block ? diagram
? ? high \ efficiency ? 5v ? mosfet ? gate ? driver ? CHL8505 ? december ? 6, ? 2011 ?? | ?? final ? | ?? v1.05 4 typical ? application ? diagram ? ? +3.3v v_cpu_l1 3 28 4 5 6 16 9 chl8325a 8 11 21 22 23 24 vinsen pwm4 pwm5 pwm3 pwm 2 pwm1 isen5 vr_rdy_l1 1 /pwrgd 2 vsen vcc rres en v18a vrtn irtn3 isen4 2 1 39 irtn1 rcsp irtn2 rcsm isen3 isen2 isen1 irtn4 +12v en l o a d rcs ccs r series r series r th r vin_1 r vin_2 37 38 35 36 33 34 irtn5 25 31 32 10 vr_rdy_l2 1 /pwrok 2 tsen r th2 7 gnd 40 20 var_gate_ pm_addr v_cpu_l2 l o a d 15 vr_hot# 1 / vrhot_icrit# 2 17 +3.3v 18 19 smb_clk smb_dio smb_alert# 29 30 rcsp_l2 rcsm_l2 rcs ccs r series r series r th 27 26 vsen_l2 vrtn_l2 17 18 19 sv_clk 1 /svc 2 sv_dio 1 /svd 2 sv_alert# 1 /vfixen 2 notes 1 pin definition in intel & mpol modes 2 pin definition in amd mode vdrv logate higate vcc gnd pwm 5v boot switch CHL8505 v 12v vdrv logate higate vcc gnd pwm 5v boot switch CHL8505 v 12v vdrv logate higate vcc gnd pwm 5v boot switch CHL8505 v 12v vdrv logate higate vcc gnd pwm 5v boot switch CHL8505 v 12v vdrv logate higate vcc gnd pwm 5v boot switch CHL8505 v 12v ? figure ? 5: ? 4+1 ? cpu ? vr ? solution ? using ? CHL8505 ? mosfet ? drivers ? & ? chl8325a ? controller
? ? high \ efficiency ? 5v ? mosfet ? gate ? driver ? CHL8505 ? december ? 6, ? 2011 ?? | ?? final ? | ?? v1.05 5 pin ? descriptions ? pin# pin name pin description 1 ? pwm ? the ? pwm ? signal ? is ? the ? control ? input ? for ? the ? driver ? from ? a ? 1.8v ? ir ? atl \ based ? pwm ? signal. ? connect ? this ? pin ? ? to ? the ? pwm ? output ? of ? the ? controller. ? 2 ? vcc ? connect ? this ? pin ? to ? a ? +5v ? bias ? supply. ? place ? a ? high ? quality ? low ? esr ? ceramic ? capacitor ? from ? this ? pin ? to ? gnd. ? 3 ? vdrv ? connect ? this ? pin ? to ? a ? separate ? supply ? voltage ? between ? 4.0v ? and ? 13.2v ? to ? vary ? the ? drive ? voltage ? on ? the ?? low \ side ? mosfets. ? place ? a ? high ? quality ? low ? esr ? ceramic ? capacitor ? from ? this ? pin ? to ? gnd. ? 4 ? nc ? leave ? this ? pin ? floating. ? 5 ? boot ? floating ? bootstrap ? supply ? pin ? for ? the ? upper ? gate ? drive. ? connect ? the ? bootstrap ? capacitor ? between ? this ? pin ? and ?? the ? switch ? pin. ? the ? bootstrap ? capacitor ? provides ? the ? charge ? to ? turn ? on ? the ? upper ? mosfet. ? see ? the ? internal ? bootstrap ? device ? section ? under ? description ? for ? guidance ? in ? choosing ? the ? capacitor ? value. ? 6 ? hi_gate ? upper ? gate ? drive ? output. ? connect ? to ? gate ? of ? high \ side ? power ? n \ channel ? mosfet. ? 7 ? switch ? connect ? this ? pin ? to ? the ? source ? of ? the ? upper ? mosfet ? and ? the ? drain ? of ? the ? lower ? mosfet. ?? this ? pin ? provides ? a ? return ? path ? for ? the ? upper ? gate ? drive ? 8 ? lo_gate ? lower ? gate ? drive ? output. ? connect ? to ? gate ? of ? the ? low \ side ? power ? n \ channel ? mosfet. ? 9 ? nc ? leave ? this ? pin ? floating. ? 10 ? nc ? leave ? this ? pin ? floating. ? pad ? (11) ? gnd ? bias ? and ? reference ? ground. ? all ? signals ? are ? referenced ? to ? this ? node. ? it ? is ? also ? the ? power ? ground ? return ?? of ? the ? driver. ?
? ? high \ efficiency ? 5v ? mosfet ? gate ? driver ? CHL8505 ? december ? 6, ? 2011 ?? | ?? final ? | ?? v1.05 6 absolute ? maximum ? ratings ? ? vcc, ? vdrv ? \ 0.3v ?? to ?? +7.0v ? pwm, ? otset, ? ot# ?\ 0.3v ?? to ?? +7.0v ? boot \ gnd, ? boot \ switch ? \ 0.3v ?? to ?? +35.0v, ?\ 0.3v ?? to ?? +7v ? lo_gate ?\ 0.3v ?? to ?? vdrv ? + ? 0.3v, ? <200ns: ?\ 5v ?? to ?? vdrv ? + ? 0.3v ? hi_gate ? switch ? ? ? 0.3v ?? to ?? vboot ? + ? 0.3v, ? <20ns: ? switch ? ?5v ?? to ?? vboot ? + ? 0.3v ? switch ?\ 0.3v ?? to ?? +35.0v, ? <200ns, ?\ 8v ? esd ? hbm ? 250v ? jedec ? standard ? thermal ? information ? ? thermal ? resistance ? ( jc ) ? 3c/w ? thermal ? resistance ? ( ja ) 1 ? 45c/w ? maximum ? operating ? junction ? temperature ? 150c ? maximum ? storage ? temperature ? range ?\ 65c ?? to ?? 150c ? maximum ? lead ? temperature ? (soldering ? 10s) ?? 300c ? note: ? 1. ? ja ? is ? measured ? with ? the ? component ? mounted ? on ? a ? high ? effective ? thermal ? conductivity ? test ? board ? in ? free ? air. ? stresses ? beyond ? those ? listed ? under ? ?absolute ? maximum ? ratings? ? may ? cause ? permanent ? damage ? to ? the ? device. ? these ? are ? stress ? ratings ? only ? and ? functional ? operation ? of ? the ? device ? at ? these ? or ? any ? other ? conditions ? beyond ? those ? indicated ? in ? the ? operational ? sections ? of ? the ? specifications ? are ? not ? implied. ?
? ? high \ efficiency ? 5v ? mosfet ? gate ? driver ? CHL8505 ? december ? 6, ? 2011 ?? | ?? final ? | ?? v1.05 7 electrical ?? specifications ? recommended ? operating ? conditions ? for ? reliable ? operation ? with ? margin ? recommended ? operating ? ambient ? temperature ? range ?\ 40c ?? to ?? 85c ? recommended ? maximum ? operating ? junction ? temperature ?? 125c ? supply ? voltage ? range ? +5v ?? ?? 10% ? ? the ? electrical ? characteristics ? table ? lists ? the ? spread ? of ? values ? guaranteed ? within ? the ? recommended ? operating ? conditions. ? typical ? values ? represent ? the ? median ? values, ? which ? are ? related ? to ? 25c, ? unless ? otherwise ? specified. ? vcc ? = ? 5.0v, ? hvcc ? = ? 7.0v, ? lvcc ? = ? 5.0v. ? electrical ? characteristics ? parameter ? symbol ? conditions ? min ? typ ? max ? unit ? supply ? ?? ? idle ? supply ? bias ? current ? i vcc ? + ? i vdrv ? pwm ? input ? tri \ stated ?\? 2.3 ?\?? ma ? active ? supply ? bias ? current ? i vcc ? vcc ? = ? 5v ? 2.7 ? 3.1 ? 3.5 ? ma ? vcc ? rising ? threshold ? for ? por ???? 3.5 ? 3.7 ? 3.9 ? v ? vcc ? falling ? threshold ? for ? por ??? 3.2 ? 3.4 ? 3.6 ? v ? pwm ? input ? ir ? atl ? mode ? ?? ?? pwm ? input ? high ? threshold ? v ih(c_pwm) ??? \? 1.0 ?\? v ? pwm ? input ? low ? threshold ? v il(c_pwm) ??? \? 0.8 ?\? v ? pwm ? input ? tri \ level ? high ? threshold ? v tl(c_pwm) ??? \? 2.5 ? \\? v ? pwm ? input ? tri \ level ? low ? threshold ? v th(c_pwm) ??? \? 2.3 ?\? v ? pwm ? input ? current ? low ? i c_pwm ? v pwm ? = ? 0v ?\? 1.0 ?\? ma ? pwm ? input ? current ? high ?? ? v pwm ? = ? 1.8v ?\? 1.0 ?\? ma ? high \ side ? gate ? driver ? transition ? time ? ? ? rise ? t r(hs) ? 3nf ? load, ? 10% ? ? ? 90% ?\? 10 ?\? ns ? transition ? time ? ? ? fall ? t f(hs) ? 3nf ? load, ? 10% ? ? ? 90% ?\? 8 ?\? ns ? propagation ? delay ? ? ? turn \ on ? t pdh(hs) ? 3nf ? load, ? adaptive ?\? 19 ?\? ns ? propagation ? delay ? ? ? turn \ off ? t pdl(hs) ? 3nf ? load ?\? 20 ?\? ns ? propagation ? delay ? ? ? exit ? tri \ state ? t pdts(hs_en) ? 3nf ? load ?\? 35 ?\? ns ? propagation ? delay ? ? ? enter ? tri \ state ? t pdts(hs_dis) ? 3nf ? load ?\? 20 ?\? ns ? source ? current ? i hs_source ? 3nf ? load ?\? 2 ?\? a ? output ? impedance ? sourcing ? r hs_source ? sink ? current ? at ? 100ma ?\? 1.4 ? \? ?? sink ? current ? i hs_sink ? 3nf ? load ?\? 2 ?\? a ? output ? impedance ? ? ? sinking ? r hs_sink ? sink ? current ? at ? 100ma ?\? 0.7 ?\??? low \ side ? gate ? driver ? transition ? time ? ? ? rise ? t f(ls) ? 3nf ? load, ? 10% ? ? ? 90% ?\? 10 ?\? ns ? transition ? time ? ? ? fall ? t r(ls) ? 3nf ? load, ? 10% ? ? ? 90% ?\? 7 ?\? ns ?
? ? high \ efficiency ? 5v ? mosfet ? gate ? driver ? CHL8505 ? december ? 6, ? 2011 ?? | ?? final ? | ?? v1.05 8 parameter ? symbol ? conditions ? min ? typ ? max ? unit ? propagation ? delay ? ? ? turn \ on ? t pdh(ls) ? 3nf ? load, ? adaptive ?\? 9 ?\? ns ? propagation ? delay ? ? ? turn \ off ? t pdl(ls) ? 3nf ? load ?\? 25 ?\? ns ? propagation ? delay ? ? ? exit ? tri \ state ? t pdts(ls_en) ? 3nf ? load ?\? 36 ?\? ns ? propagation ? delay ? ? ? enter ? tri \ state ? t pdts(ls_dis) ? 3nf ? load ?\? 22 ?\? ns ? source ? current ? i ls_source ? 3nf ? load ?\? 2 ?\? a ? output ? impedance ? sourcing ? r ls_source ? sink ? current ? at ? 100ma ? \? 1.5 ? \? ?? sink ? current ? i ls_sink ? 3nf ? load ? \? 4 ? \? a ? output ? impedance ? ? ? sinking ? r ls_sink ? sink ? current ? at ? 100ma ? \? 0.4 ? \? ?? note: ? 1 ? guaranteed ? by ? design ?
? ? high \ efficiency ? 5v ? mosfet ? gate ? driver ? CHL8505 ? december ? 6, ? 2011 ?? | ?? final ? | ?? v1.05 9 timing ? diagram ? ? ? ? figure ? 6: ? ir ? active ? tri \ level ? (atl) ? mode ? pwm, ? hi_gate ? and ? lo_gate ? signals normal pwm operation active tri-level (atl) pwm operation hi_gate lo_gate pwm r(hs) pdts(hs_en) t pdl ( hs ) t t f ( hs) t f( ls) t r(ls) t pdl ( ls ) t pdh(ls) t pdts ( ls _ dis ) t t pdl ( hs ) t pdts ( hs _ dis ) t pdts ( ls _ en )
? ? high \ efficiency ? 5v ? mosfet ? gate ? driver ? CHL8505 ? december ? 6, ? 2011 ?? | ?? final ? | ?? v1.05 10 general ? description ? ? the ? CHL8505 ? is ? a ? high ? efficiency, ? fast ? mosfet ? driver ? with ? large ? source ? and ? sink ? current ? capability. ? it ? can ? reliably ? drive ? the ? external ? high \? and ? low \ side ? n \ channel ? mosfets ? with ? large ? input ? capacitance ? at ? switching ? frequencies ? up ? to ? 1mhz. ? the ? patented ? ir ? active ? tri \ level ? (atl) ? feature ? allows ? complete ? control ? over ? enable ? and ? disable ? of ? both ? mosfets ? using ? the ? pwm ? input ? signal ? from ? the ? controller. ? the ? timing ? and ? voltage ? levels ? of ? atl ? are ? shown ? in ? figure ? 6. ?? during ? normal ? operation ? the ? pwm ? transitions ? between ? low ? and ? high ? voltage ? levels ? to ? drive ? the ? low \? and ? high \ side ? mosfets. ? the ? pwm ? signal ? falling ? edge ? transition ? to ? a ? low ? voltage ? threshold ? initiates ? the ? high \ side ? driver ? turn ? off ? after ? a ? short ? propagation ? delay, ? t pdl(hs) . ? the ? dead ? time ? control ? circuit ? monitors ? the ? hi_gate ? and ? switch ? voltages ? to ? ensure ? the ? high \ side ? mosfet ? is ? turned ? off ? before ? the ? lo_gate ? voltage ? is ? allowed ? to ? rise ? to ? turn ? on ? the ? low \ side ? mosfet. ?? the ? pwm ? rising ? edge ? transition ? through ? the ? high \ side ? turn ? on ? threshold, ? initiates ? the ? turn ? off ? of ? the ? low \ side ? mosfet ? after ? a ? small ? propagation ? delay, ? t pdl(ls) . ? the ? adaptive ? dead ? time ? circuit ? provides ? the ? appropriate ? dead ? time ? by ? determining ? if ? the ? falling ? lo_gate ? voltage ? threshold ? has ? been ? crossed ? before ? allowing ? the ? hi_gate ? voltage ? to ? rise ? and ? turn ? on ? the ? high \ side ? mosfet, ? t pdh(hs) . ? . ?
? ? high \ efficiency ? 5v ? mosfet ? gate ? driver ? CHL8505 ? december ? 6, ? 2011 ?? | ?? final ? | ?? v1.05 11 theory ? of ? operation ? ? power \ on ? reset ? (por) ? the ? CHL8505 ? incorporates ? a ? power \ on ? reset ? feature. ?? this ? ensures ? that ? both ? the ? high \? and ? low \ side ? output ? drivers ? are ? made ? active ? only ? after ? the ? device ? supply ? voltage ? has ? exceeded ? a ? certain ? minimum ? operating ? threshold. ? the ? v cc ? and ? v drv ? supply ? is ? monitored ? and ? both ? the ? drivers ? are ? set ? to ? the ? low ? state, ? holding ? both ? external ? mosfets ? off. ? once ? v cc ? and ? v drv ? crosses ? the ? rising ? por ? threshold, ? the ? CHL8505 ? is ? reset ? and ? the ? outputs ? are ? held ? in ? the ? low ? state ? until ? a ? transition ? from ? tri \ state ? to ? active ? operation ? is ? detected ? at ? the ? pwm ? input. ? during ? normal ? operation ? the ? drivers ? continue ? to ? remain ? active ? until ? the ? v cc ? and ? v drv ? falls ? below ? the ? falling ? por ? threshold. ?? integrated ? bootstrap ? diode ? the ? CHL8505 ? features ? an ? integrated ? bootstrap ? diode ? to ? reduce ? external ? component ? count. ? this ? enables ? the ? CHL8505 ? to ? be ? used ? effectively ? in ? cost ? and ? space ? sensitive ? designs. ? the ? bootstrap ? circuit ? is ? used ? to ? establish ? the ? gate ? voltage ? for ? the ? high \ side ? driver. ? it ? consists ? of ? a ? diode ? and ? capacitor ? connected ? between ? the ? switch ? and ? boot ? pins ? of ? the ? device. ? integrating ? the ? diode ? within ? the ? CHL8505, ?? results ? in ? the ? need ? for ? an ? external ? boot ? capacitor ? only. ?? the ? bootstrap ? capacitor ? is ? charged ? through ? the ? diode ?? and ? injects ? this ? charge ? into ? the ? high \ side ? mosfet ? input ? capacitance ? when ? pwm ? signal ? goes ? high. ?? ir ? active ? tri \ level ? (atl) ? pwm ? input ? signal ? the ? CHL8505 ? gate ? drivers ? are ? driven ? by ? a ? patented ? tri \ level ? pwm ? control ? signal ? provided ? by ? the ? ir ? digital ? pwm ? controllers. ? during ? normal ? operation, ? the ? rising ? and ? falling ? edges ? of ? the ? pwm ? signal ? transitions ? between ? 0v ? and ? 1.8v ? to ? switch ? the ? lo_gate ? and ? hi_gate. ? to ? force ? both ? driver ? outputs ? low ? simultaneously, ? the ? pwm ? signal ? crosses ? a ?? tri \ state ? voltage ? level ? higher ? than ? the ? tri \ state ? hi_gate ? threshold. ? this ? threshold ? based ? tri \ state ? results ? in ? a ? very ? fast ? disable ? for ? both ? the ? drivers, ? with ? only ? a ? small ? tri \ state ? propagation ? delay. ? mosfet ? switching ? resumes ? when ? the ? pwm ? signal ? falls ? below ? the ? tri \ state ? threshold ? into ? the ? normal ? operating ? voltage ? range. ?? this ? fast ? tri \ state ? operation ? eliminates ? the ? need ? for ? any ?? tri \ state ? hold \ off ? time ? of ? the ? pwm ? signal ? to ? dwell ? in ? the ? shutdown ? window. ? dedicated ? disable ? or ? enable ? pins ? are ? not ? required ? which ? simplifies ? the ? routing ? and ? layout ? in ? applications ? with ? a ? limited ? number ? of ? board ? layers. ? it ? also ? provides ? switching ? free ? of ? shoot ? through ? for ? slow ? pwm ? transition ? times ? of ? up ? to ? 20ns. ? the ? CHL8505 ? is ? therefore ? tolerant ? of ? stray ? capacitance ? on ? the ? pwm ? signal ? lines. ? the ? CHL8505 ? provides ? a ? 1.0ma ? typical ? pull \ up ? current ? to ? drive ? the ? pwm ? input ? to ? the ? tri \ state ? condition ? of ? 3.3v ? when ? the ? pwm ? controller ? output ? is ? in ? its ? high ? impedance ? state. ? the ? 1.0ma ? typical ? current ? is ? designed ? for ? driving ? worst ? case ? stray ? capacitances ? and ? transition ? the ? CHL8505 ? into ? the ? tri \ state ? condition ? rapidly ? to ? avoid ? a ? prolonged ? period ? of ? conduction ? of ? the ? high \? or ? low \ side ? mosfets ? during ? faults. ? immediately ? after ? the ? driver ? is ? driven ? into ? the ? tri \ state ? mode, ? the ? 1ma ? current ? is ? disables ? such ? that ? power ? is ? conserved. ?? diode ? emulation ? during ? load ? release ? one ? advantage ? of ? this ? fast ? tri \ state ? scheme ? is ? the ? ability ?? to ? quickly ? turn \ off ? all ? low \ side ? mosfets ? during ? a ? load ? release ? event. ? this ? is ? known ? as ? diode ? emulation ? since ? all ? the ? load ? current ? is ? forced ? to ? flow ? momentarily ? through ?? the ? body ? diodes ? of ? the ? mosfets. ? this ? results ? in ? a ? much ? lower ? overshoot ? on ? the ? output ? voltage ? as ? can ? be ? seen ? in ? figure ? 7 ? below. ?? ? figure ? 7: ? output ? voltage ? overshoot ? reduction ?? with ? diode ? emulation ? start ? up ? during ? initial ? startup, ? the ? CHL8505 ? holds ? both ? high \? and ? low \ side ? drivers ? low ? even ? after ? por ? threshold ? is ? reached. ? this ? mode ? is ? maintained ? while ? the ? pwm ? signal ? is ? pulled ? to ? the ? tri \ state ? threshold ? level ? greater ? than ? the ? tri \ state ? hi_gate ? threshold ? and ? until ? it ? transitions ? out ? of ? tri \ state. ?? it ? is ? this ? initial ? transition ? out ? of ? the ? tri \ state ? which ? enables ? both ? drivers ? to ? switch ? based ? on ? the ? normal ? pwm ? voltage ? levels. ?? i_out 105a to 10a v_out without diode emulation overshoots ~25mv over 0a level v_out with diode emulation overshoot within 0a level results in reduction of 30mv overshoot
? ? high \ efficiency ? 5v ? mosfet ? gate ? driver ? CHL8505 ? december ? 6, ? 2011 ?? | ?? final ? | ?? v1.05 12 this ? startup ? also ? ensures ? that ? any ? undetermined ? pwm ? signal ? levels ? from ? a ? controller ? in ? pre \ por ? state ? will ? not ? result ? in ? high \? or ? low \ side ? mosfet ? turn ? on ? until ? the ? controller ? is ? out ? of ? its ? por. ? high \ side ? driver ? the ? high \ side ? driver ? drives ? an ? external ? floating ? n \ channel ? mosfet ? which ? can ? be ? switched ? at ? 1mhz. ? an ? external ? bootstrap ? circuit ? referenced ? to ? the ? switch ? node, ? consisting ? of ? a ? boot ? diode ? and ? capacitor ? is ? used ? to ? bias ?? the ? external ? mosfet ? gate. ? when ? the ? switch ? node ? is ? at ? ground, ? the ? boot ? capacitor ? is ? charged ? to ? near ? the ? supply ? voltage ? using ? the ? boot ? diode ? and ? this ? stored ? charge ? is ? used ? to ? turn ? on ? the ? external ? mosfet ? when ? the ? pwm ? signal ? goes ? high. ? once ? the ? high \ side ? mosfet ? is ? turned ? on, ? the ? switch ? voltage ? raises ? to ? the ? supply ? voltage ? and ? the ? boot ? voltage ? to ? twice ? the ? supply ? voltage. ? when ? the ? pwm ? signal ? goes ? low, ? the ? mosfet ? is ? turned ? off ? by ? pulling ? the ? mosfet ? gate ? to ? the ? switch ? voltage. ? low \ side ? driver ? the ? CHL8505 ? low \ side ? driver ? is ? designed ? to ? drive ? an ? external ? n \ channel ? mosfet ? referenced ? to ? ground ? at ? 1mhz. ? the ? low \ side ? driver ? is ? connected ? internally ? to ? the ? supply ? voltage ? to ? turn ? the ? mosfet ? on. ? when ? the ? low \ side ? mosfet ? is ? turned ? on ? the ? switch ?? node ? is ? pulled ? to ? ground. ? this ? allows ? charging ? of ? the ? boot ? capacitor ? to ? the ? supply ? voltage ? ready ? to ? drive ? the ? high \ side ? mosfet ? based ? on ? the ? pwm ? signal ? level. ? adaptive ? dead ? time ? adjustment ? in ? a ? synchronous ? buck ? configuration ? dead ? time ? between ? the ? turn ? off ? of ? one ? gate ? and ? turn ? on ? of ? the ? other ? is ? necessary ? to ? prevent ? simultaneous ? conduction ? of ? the ? external ? mosfets. ? it ? prevents ? a ? shoot \ through ? condition ? which ? would ? result ? in ? a ? short ? of ? the ? supply ? voltage ? to ? ground. ? a ? fixed ? dead ? time ? does ? not ? provide ? optimal ? performance ? over ? a ? variety ? of ? mosfets, ? converter ? duty ? cycles ? and ? board ? layouts. ? the ? CHL8505 ? provides ? an ? ?adaptive? ? dead ? time ? adjustment. ? this ? feature ? minimizes ? dead ? time ? to ? an ? optimum ? duration ? which ? allows ? for ? maximum ? efficiency. ? the ? ?break ? before ? make? ? adaptive ? design ? is ? achieved ? by ? monitoring ? gate ? and ? switch ? voltages ? to ? determine ? off ? status ? of ? a ? mosfet. ?? it ? also ? provides ? zero \ voltage ? switching ? (zvs) ? of ? the ? low \ side ? mosfet ? with ? minimum ? current ? conduction ? through ? its ? body \ diode. ?? when ? the ? pwm ? is ? switching ? between ? 1.8v ? and ? 0v, ? its ? falling ? edge ? transition ? from ? high ? to ? low ? will ? turn ? off ? the ? high \ side ? gate ? driver. ? the ? adaptive ? dead ? time ? circuit ? monitors ? the ? hi_gate ? and ? the ? switch ? node ? voltages ? during ? the ? high \ side ? mosfet ? turn ? off. ? when ? the ? hi_gate ? falls ? below ? 1.7v ? above ? the ? switch ? node ? potential ? or ? the ? switch ? node ? voltage ? drops ? below ? 0.8v ? the ? high \ side ? mosfet ? is ? determined ? to ? be ? turned ? off ? and ? the ? lo_gate ? turn ? on ? is ? initiated. ? this ? turns ? on ? the ? external ? low \ side ? mosfet. ? the ? rising ? edge ? transition ? of ? the ? pwm ? signal ? from ? low ? to ? high ? voltage ? causes ? the ? low \ side ? gate ? driver ? to ? turn ? off. ? the ? adaptive ? circuit ? monitors ? the ? voltage ? at ? lo_gate ? and ? when ? it ? falls ? below ? 1.7v, ? the ? low \ side ? mosfet ? is ? determined ? to ? be ? turned ? off ? and ? the ? high \ side ? mosfet ? turn ? on ? is ? initiated. ? ?
? ? high \ efficiency ? 5v ? mosfet ? gate ? driver ? CHL8505 ? december ? 6, ? 2011 ?? | ?? final ? | ?? v1.05 13 application ? information ? ? boot ? strap ? circuit ? once ? the ? high \ side ? mosfet ? selection ? is ? made, ? the ? bootstrap ? circuit ? can ? be ? defined. ? the ? integrated ? boot ?? diode ? of ? the ? CHL8505 ? reduces ? the ? external ? component ? count ? for ? use ? in ? cost ? and ? space ? sensitive ? designs. ? for ? ultra ? high ? efficiency ? designs, ? an ? external ? boot ? strap ? diode ? is ? recommended. ?? the ? bootstrap ? capacitor ? c boot ? stores ? the ? charge ? and ? provides ? the ? voltage ? required ? to ? drive ? the ? external ? high \ side ? mosfet ? gate. ? the ? minimum ? capacitor ? value ? can ? be ? defined ? by: ? c boot ? = ? q hs ? mosfet_gate ? / ?? v boot ? where, ?? ? q hs ? mosfet_gate ? is ? the ? total ? gate ? charge ? of ? the ?? high \ side ? external ? mosfet(s) ?? ? ? v boot ? is ? the ? droop ? allowed ? on ? the ? boot ? capacitor ? voltage ? (at ? the ? high \ side ? mosfet ? gate) ? a ? series ? resistor, ? 1 ? to ? 4 , ? may ? be ? added ? to ? customize ? the ? rise ? time ? of ? the ? high \ side ? output. ? slowing ? down ? this ? output ? allows ? setting ? the ? phase ? node ? rising ? slew ? rate ? and ? limits ? the ? surge ? current ? into ? the ? boot ? capacitor ? on ? start \ up. ? supply ? decoupling ? capacitor ? vcc ? decoupling ? to ? the ? ir3598 ? is ? provided ? by ? a ? 0.1uf ? bypass ? capacitor ? c vcc ? located ? close ? to ? the ? supply ? input ? pin. ? a ? series ? resistor ? rvcc, ? typically ? 10 , ? is ? added ? in ? series ? with ? the ? supply ? voltage ? to ? filter ? high ? frequency ? ringing ? and ? noise. ? a ? 1.0uf ? or ? higher ? capacitor ? is ? recommended ? for ? the ? vdrv ? decoupling ? capacitor, ? cdrv. ?? pcb ? layout ? considerations ? pcb ? layout ? and ? design ? is ? important ? to ? driver ? performance ? in ? voltage ? regulator ? circuits ? due ? to ? the ? high ? current ? slew ? rate ? (di/dt) ? during ? mosfet ? switching. ? ? locate ? all ? power ? components ? in ? each ? phase ? as ? close ? to ? each ? other ? as ? practically ? possible ? in ? order ? to ? minimize ? parasitics ? and ? losses, ? allowing ? for ? reasonable ? airflow. ? ? input ? supply ? decoupling ? and ? bootstrap ? capacitors ? should ? be ? physically ? located ? close ? to ? their ? respective ? ic ? pins. ? ? high ? current ? paths ? like ? the ? gate ? driver ? traces ? should ? be ? as ? wide ? and ? short ? as ? practically ? possible. ? ? trace ? inductances ? to ? the ? high \? and ? low \ side ? mosfets ? should ? be ? minimized. ? ? the ? ground ? connection ? of ? the ? ic ? should ? be ? as ? close ? as ? possible ? to ? the ? low \ side ? mosfet ? source. ? ? use ? of ? a ? copper ? plane ? under ? and ? around ? the ? ic ?? and ? thermal ? vias ? to ? connect ? to ? buried ? copper ? layers ? improves ? the ? thermal ? performance. ?? mosfet ? stages ? should ? be ? well ? bypassed ? with ? capacitors ? placed ? between ? the ? drain ? of ? the ? high \ side ? mosfet ? and ? the ? source ? of ? the ? low \ side ? mosfet.
? ? high \ efficiency ? 5v ? mosfet ? gate ? driver ? CHL8505 ? december ? 6, ? 2011 ?? | ?? final ? | ?? v1.05 14 marking ? information ? ? ? ? ? ? ? ? ? figure ? 8: ? package ? marking ? package ? information ?? dfn ? 3x3mm, ? 10 ? pin ? ? figure ? 9: ? package ? dimensions assembler/date code 8505 zzz-xx a yyww pin 1 part number lot # & wafer code
? ? high \ efficiency ? 5v ? mosfet ? gate ? driver ? CHL8505 ? december ? 6, ? 2011 ?? | ?? final ? | ?? v1.05 15 ? data ? and ? specifications ? subject ? to ? change ? without ? notice. ? this ? product ? will ? be ? designed ? and ? qualified ? for ? the ? consumer ? market. ? qualification ? standards ? can ? be ? found ? on ? ir?s ? web ? site. ? ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . www.irf.com ?

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